Device Modeling Toolkit

Semiconductor device modeling engineers are faced by a number of non-trivial tasks that can be solved efficiently using software. We created the Python toolkit DMT for conducting our modeling service and also share it with our customers.

DMT is written and used by SemiMod, hence it is perfectly suited for:

  • Measurement data management
  • Circuit and TCAD simulation control
  • Processing of device modelcards
  • Extraction of model parameters
  • Generation of high-quality PDF measurement and extraction reports

The core module of DMT is free to use and can be obtained, installed, and used by everyone, and is licensed via GPL-v3. The core modules include data management, and model handling via the VerilogAE compiler, and some circuit simulator interfaces.

If you’re looking to control your simulator from within Python and to increase its versatility, have a look at our source code.

DMT Interfacing a simulator

SemiMod can assist you in interfacing your simulator using DMT.

Release Paper

Paper published in Journal of Open Source Software


Python package documentation, including installation and examples.

Source code

Repository with the full source code.


All package releases, including release candidates. Full releases can be obtained via pip from PyPi.

The full DMT project including parameter extraction flows for advanced compact models is available for our partners only. We can assist in writing new extraction routines upon request.

Our partners are
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OpenVAF, OSDI and VerilogAE

Verilog-A is the industry-standard language for implementing compact models. Existing solutions have many shortcomings and even struggle to compile the Silicon Integration Initiative Compact Model Coalition standard models. While CMC models are always implemented in Verilog-A, most users do not actually use that Verilog-A code. Instead, circuit simulators manually implement each model in a labor-intensive and error-prone process. Furthermore, advanced tooling that is useful for parameter extraction or research has not been available so far. Surprisingly, there does not exist an industry-standard Verilog-A compiler.

SemiMod has developed a state-of-the-art compiler to provide the next generation of Verilog-A software infrastructure.  Our aim is to bring the advancements made in compiler-construction for other languages to Verilog-A. Our solution consists of 3 components:

  • OpenVAF: Flexible general purpose Verilog-A compiler
  • OSDI: Simulator-independent model interface (under development)
  • VerilogAE: Python library for interfacing Verilog-A

If your circuit simulation environment needs a state-of-the-art Verilog-A compiler, contact us, and we will help to integrate OpenVAF into your simulation workflow.

OpenVAF – General Purpose Verilog-A Compiler

OpenVAF with general backend

OpenVAF forms the core of our technology stack. It is a general purpose Verilog-A compiler with a flexible and modern architecture. This allows it to be used as a standalone executable for compiling Verilog-A models. Compared to traditional compilers, OpenVAF provides a better user experience by offering:

  • Helpful diagnostics
  • more comprehensive standard compliance
  • faster compilation and simulation using cutting edge automatic differentiation technology

OpenVAF takes implements high quality diagnostic messages that provide detailed information to users. Furthermore, OpenVAF is designed to be error resilient. This allows the compiler to detect all errors at once, instead of aborting after a single error, like other compilers do.

Another important component of the user-experience is documentation.
The documentation of Verilog-A already exists in the form of the language standard.  To ensure consistent behavior, OpenVAF aims to closely implement the language standard, where possible. For example, OpenVAF is able to correctly compile all CMC models without modification and handle higher-order derivatives. However, due to limitations of most circuit simulators, some features can not be supported sometimes. SemiMod is committed to ensuring that in these cases helpful diagnostics are emitted by OpenVAF and to document these deviations.

The most important improvement offered by OpenVAF is the improvement in compilation and simulation speed.  OpenVAF internally functions more like a C-compiler compared to traditional Verilog-A compilers that actually are transpilers. As a result, it avoids lots of repeated numeric effort and can compile (almost) all CMC models in less than 2 seconds. This approach also allows more complex analysis algorithms which allow OpenVAF to generate much more numerically efficient derivatives, simulators that leverage OpenVAF can expect an improvement of the model`s evaluation speed of around 30%-300% compared to traditional compilers. OpenVAF compiled models match and exceed the speed of handwritten models.


OpenVAF with OSDI backend

OSDI is a simulator independent interface for device models. OpenVAF compiles Verilog-A files to shared libraries that conform to OSDI. The interface is designed to be modular, so it can be used regardless of the details of the simulators. Compared to traditional compilers, different simulators won’t have to re implement large components of the compiler, instead they can just implement a compatibility layer between OSDI and the internal interface.

SemiMod can assist you as a partner during this process.


VerilogAE is a Python library that makes individual model equations available in Python.  Compared to a circuit simulator, there is no solver involved. Instead, the user needs to provide all potential used for evaluating model equations. The intended use-case is parameter extraction or investigating model internals. DMT integrates VerilogAE directly to offer a comprehensive stack of tools for device engineers.


Repository with the full source code of OpenVAF and VerilogAE


Documentation of OpenVAF and VerilogAE


All release python packages are available on PyPi and can be obtained using pip.